A nonvolatile memory maintains stored data even though the memory does not have power for a period of time. A read only memory is a memory which contains data that can not change. Nonvolatile read only memories are very useful in computers because they provide a computer with initial instructions or data when the computer is first powered up. These memories are useful, however, the entire memory must be discarded when the initial instruction set or data is changed. Nonvolatile programmable read only memories (PROMS) are memories in which the stored instructions or data can be changed without discarding the entire memory. Typically, changing the instructions or data in a PROM required erasing the existing data with ultraviolet light and electrically reprogramming the device. This is a time consuming and difficult process and it is impractical to erase and reprogram such a device frequently. However, PROMs which are both electrically erasable and programmable are practical to erase and reprogram and, as a result, are very useful in computers or electrical devices where power is frequently interrupted. This is because the data and instructions the computer was processing can be stored when the power is interrupted and recalled when power is restored.
Electrically erasable programmable read only memories (EEPROMs) were developed in response to the need for a nonvolatile memory which could have the stored data changed on a frequent basis. FIG. 1 illustrates a prior art EEPROM cell. The EEPROM cell is a conventional FET comprised of a source, drain, and gate regions wherein the gate region has been modified to include a floating gate. The EEPROM memory is composed of an array of EEPROM cells identical to the cell of FIG. 1. The array is organized into columns of devices connected to individual bit lines and rows of devices connected to individual word lines. Each cell is addressed by energizing the bit lines (B/L) 18 and 18' and the word line (W/L) 20 attached to a particular memory cell in the array. The W/L 20 forms a control gate 10 over each cell in the array. The control gate 10 covers a first insulator layer 8 which covers a floating gate 6 which covers the channel region 4 of the cell device. The bit lines 18 and 18' are connected to the drain 16 and source 14 respectively of the cell device. The drain 16 and the source 14 are both typically an n-type regions (but can be p-type regions).
The EEPROM device is programmed by applying a large positive voltage to the W/L 20 and B/L 18 (connected to drain 16) with respect to the voltage on the p-type substrate 2 and on the source 18'. The large voltage on the B/L 18 increases the energy of electrons in the channel region 4 close to the drain region 16. The large voltage on the control gate induces an electric field which moves the highly energetic electrons from the channel region 4 close to the drain into the floating gate 6. The presence of the electrons in the floating gate 6 alters the normal operation of the FET. Normally, a low level voltage on the gate of the FET would provide a conductive path between the drain and source regions. However, when the device has been programmed with electrons in the floating gate, the low level voltage on the control gate is not sufficient to provide the conductive path between the drain and source regions. Detecting when current flows between the drain and source regions when a low voltage is applied to the control gate 10 (through W/L 20) and B/L 18 with respect to B/L 18' indicates the state of data stored in the EEPROM cell. The floating gate 6 is erased by applying a large positive voltage on the wordline with respect to the substrate 2 (independent of the voltage on the bit line). This large voltage removes the electrons from the floating gate 6.
The problem with the prior art planar device is that it is too large in terms of surface area required to make a device which has large coupling between the floating gate and the control gate. A large coupling is required to facilitate programming and erasing at lower voltages. Decreasing the surface area of the memory cell is important because this increases the density of the memory and decreases the cost of manufacturing the memory. The prior art has attempted to solve this problem by building the EEPROM cell in a trench which decreases the surface area of the device. The channel of the device is formed on the bottom of the trench. The sidewalls of the trench form vertical capacitors which increase the area of the floating gate without increasing the surface area of the EEPROM cell itself. The problem with this prior art device is that, although the floating-gate to control-gate capacitance increases, the floating gate to substrate capacitance also increases. This means the coupling between the two capacitors does not substantially increase. The prior art devices are also too slow in programming and erasing because they use hot electron injection from the channel region into the floating gate which consumes a lot of energy so that only few cells can be programmed at a time. Merely building a device in a trench does not address the slow program and erase problem because the device is programmed and erased by an electric field applied to the channel region and floating gate.
The prior art has developed devices which decrease the time needed to program and erase the EEPROM. This has been accomplished through the use of carrier injection techniques which do not depend on injection to the floating gate from the channel region of the EEPROM cell device. In particular, the prior art describes forming a floating gate over a heavily doped drain region wherein the drain region is separated from the floating gate region by a thin dielectric layer. The thin dielectric layer allows tunneling of carriers between the drain region and the floating gate. The tunneling through the drain region both programs and erases the device. The use of this tunneling mechanism helps decrease the program and erase time because Fowler-Nordheim tunneling is a very efficient injection mechanism which allows many cells to be programmed and erased at one time. As a result, the program and erase time for any single cell is reduced. However, the formation of the thin dielectric over the drain region expands the size of the EEPROM cell. In effect, the prior art decreases the program and erase time while increasing the cell size of the EEPROM array which increases the surface area of the memory.